Integrated circuit device having pads structure formed thereon and method for forming the same

ABSTRACT

The invention is to provide a structure of IC pad and its forming method. The structure is arranged in an insulation layer and is comprised of a lower electric-conduction layer, a compound layer structure and a pad layer. The lower electric-conduction layer is arranged at an appropriate position in the insulation layer and is connected to an electric potential. The compound layer structure is arranged on the insulation layer and is composed of at least one electric-conduction layer and at least one electric-conduction connecting layer, both are inter-overlapped to each other. The pad layer is arranged on the compound layer structure.

This application is a continuation application of U.S. patentapplication Ser. No. 14/743,421, filed Jun. 18, 2015, which is a reissueapplication of U.S. patent application Ser. No. 10/425,973, filed Apr.30, 2003, now U.S. Pat. No. 6,787,928, issued Sep. 7, 2004, which claimspriority from Taiwanese Patent Application No. 92104606, filed on Feb.26, 2003, the disclosure of which is incorporated herein by reference inits entirety. This application is also a reissue application of U.S.Pat. No. 6,787,928.

FIELD OF THE INVENTION

The invention relates to a structure of IC pad and its forming method,in particular to a structure and method that are adapted to form a padof integrated circuit of high frequency and low noise; not only thenoise from the semiconductor substrate be separated effectively and thevalue of equivalent electric capacitance of the pad be lowered, but alsothe bonding adherence be further enhanced.

BACKGROUND OF THE INVENTION

Recently, since the requirement of transceiver of low power and low costis steadily on the increase, so the technology of mainstream ICcompetitively concentrates on how to realize further more functions ofradio frequency on one single chip. Except making integrated circuit beable to arrange on the package substrate, the external circuit connectedby the external legs of package substrate must be electrically connectedto the integrated circuit. So, when packaging the integrated circuit,the technology of pad has become an important factor that influences theyield and quality of a product. This pad adapted for providing electricconnection between the integrated circuit and the external circuit isusually arranged in the metal zone around the IC die. When the pad isformed, the metal connecting wire must contact with the pad accuratelyand connect to the external legs of the IC packaging substrate. Becauseof the limitation of the prior arts and the characteristics of metalconnecting wire and pad, the area of pad is sometimes too large tooccupy too much area of chip. Furthermore, during high frequency, theperformance of the integrated circuit is influenced because theequivalent electric capacitance is too large.

Additionally, because of the market growth of communication IC recently,the operational frequency of integrated circuit is also growing inindexing type. The low noise and low loss of high frequency signal arealways the pursuing goals for communication IC.

In 1987, the U.S. Pat. No. 4,636,832 “Semiconductor device with animproved bonding section” proposed a design method of the pad ofintegrated circuit. Please refer to FIG. 1, which is a cross-sectionaldiagram of the IC device disclosed in the U.S. Pat. No. 4,636,832. Thecharacteristic of this prior art is that the semiconductor element 10 isarranged below the pad 15. Although it may reduce the area of layout,this kind of pad can not be adapted to high frequency circuit with lownoise because the noise coming from the semiconductor substrate 20 willdirectly influence the signal of high frequency when it passes throughthe pad.

To overcome the tensile and tension of bonding, the U.S. Pat. No.5,248,903 “Composite pads for semiconductor devices” proposed a kind ofpad. Please refer to FIG. 2, which is the cross-sectional diagram of theIC device disclosed in the U.S. Pat. No. 5,248,903. Wherein, the pad 30has at least two layers of electric-conduction layer 30a and 30c and aconnection layer 30b. But, this kind of pad is not adapted for thesignals of high frequency and low noise because the noise ofsemiconductor substrate 35 will directly influence the quality ofsignal.

The U.S. Pat. No. 5,502,337 “Semiconductor device structure includingmultiple interconnection layers with interlayer insulating films”proposed a different designing method for pad. Please refer to FIG. 3,which is a cross-sectional diagram for the IC device disclosed in theU.S. Pat. No. 5,502,337, which arranges the connection layer 40a in thepad 40 around the bonding zone 45. When the integrated circuit ismanufactured, a bonding zone of arc shape will be formed on the pad 40to thereby enhance the bonding adherence. However, the technology ofcurrent integrated circuit has stepped into the levels of sub micrometeror deep sub micrometer, and CMP (Chemical-Mechanical Polish) is alreadya standard procedure for current semiconductor process. So, this kind ofprior art no longer generates original effectiveness in currentsemiconductor process, besides this technique has the same drawback asthat of previous techniques; i.e., it can not separate the noise comingfrom the semiconductor substrate 50.

From above discussion, we know that the prior arts described there areunable to propose an effective solution that aims for the highfrequency, low noise and bonding adherence. Therefore, the emphasis ofthe invention is to provide a pad structure adapted for a integratedcircuit of high frequency and low noise to lower down the equivalentelectric capacitance and enhance the bonding adherence, such that it canprevent the entire pad from being drawn out of the semiconductor chip bythe tension generated in the bonding procedure.

SUMMARY OF THE INVENTION

The main objective of the present invention is to provide a structure ofIC pad and its forming method, which are adapted for the structure ofthe pad of an integrated circuit of high frequency and low noise, suchthat the effective area of the pad may be reduced effectively to therebyreduce its value of equivalent electric capacitance.

The second objective of the present invention is to provide a structureof IC pad and its forming method effectively separate the noise comingfrom the semiconductor substrate.

The further objective of the present invention is to provide a structureof IC pad and its forming method effectively enhance the bondingadherence, such that it prevent the entire pad from being drawn out ofthe semiconductor chip by the tension generated in the bondingprocedure.

To achieve above objectives, the invention provides an IC pad structurearranged in an insulation layer comprises a lower electric-conductionlayer, a compound layer structure and a pad layer.

The lower electric-conduction layer is arranged in the insulation layerand is connected to an electric potential.

The compound layer structure arranged on the insulation layer comprisesat least one electric-conduction layer and at least oneelectric-conduction connecting layer, each of the electric-conductionlayer are connected to each other.

The pad layer is arranged on the compound layer structure.

To achieve above objectives, the invention further presents method forforming IC pad structure, comprising the following steps of:

Step (a): providing a substrate arranged with an insulation layer.

Step (b): forming a lower electric-conduction layer which preparedconnect to an electric potential.

Step (c): forming a compound layer structure composed byinter-overlapping or connect at least one electric-conduction layer andat least one electric-conduction connecting layer on the insulationlayer.

Step (d): forming a pad layer on the compound layer structure, of whicharea is larger than that of the electric-conduction layer of thecompound layer structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional diagram for the IC device disclosed in theU.S. Pat. No. 4,636,832.

FIG. 2 is a cross-sectional diagram for the IC device disclosed in theU.S. Pat. No. 5,248,903.

FIG. 3 is a cross-sectional diagram for the IC device disclosed in theU.S. Pat. No. 5,502,337.

FIG. 4 is an upper side view for the structural illustration of apreferable embodiment of the IC pad according to the invention.

FIG. 5 is a cross-sectional view along the A-A line cutting through FIG.4 illustrating the preferable embodiment of the IC pad according to theinvention.

FIG. 6 is a flowchart illustrating the preferable embodiment of themethod forming the IC pad according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

For your esteemed member of reviewing committee to further recognize andunderstand the characteristics, objectives, and functions of the presentinvention, a detailed description together with corresponding drawingsare presented thereinafter.

The invention discloses a structure of IC pad and its forming method.Its embodiments are described according to referential drawings, inwhich similar referential numbers represent similar elements.

Please refer to FIG. 4 and FIG. 5, which are structural illustrationsfor the preferable embodiments of the IC pad according to the presentinvention. The IC pad structure includes a lower electric-conductionlayer 300, a compound layer structure 100, and a first pad layer 600.The lower electric-conduction layer 300 formed at an appropriateposition in the insulation layer 500 is coupled with pluralelectric-conduction layers 202 and plural electric-conduction connectinglayers 201, shown in FIG. 5, such that the lower electric-conductionlayer 300 may a voltage signal from a second pad layer 700 formed on theupper surface exposing on the insulation layer 500 through provideelectric-conduction layers 202 and electric-conduction connecting layers201 shown in FIG. 5, which further provides a connection to a deviceproviding the voltage signal (not shown in the drawings). The second padlayer 700 further forms a bonding zone with a chip passivation layer 205and 105. The noise transferred from the substrate 40 400 will be keptaway by the lower electric-conduction layer 300 which may be connectedto a power source or voltage signal by the second pad layer 700.

The compound layer structure 100 is arranged on the insulation layer 500and is composed of at least one electric-conduction layer 102 and atleast one electric-conduction connecting layer 101, both which areinter-overlapped to each other. The pad layer 600 is arranged on thecompound layer structure 100 and is adjacent to the top face side of theinsulation layer 500. In the preferable embodiments according to theinvention and in order to lower down the value of the effectivecapacitance of the entire pad, the pad layer 600 is realized by thestructuring method of polygon shape and the area of theelectric-conduction layer 102 is designed to be smaller than that of thepad layer 600, such that the value of the equivalent electriccapacitance to the lower electric-conduction layer 300 may be furthereffectively lowered down. The electric-conduction layer 102 may berealized by the methods of railing structure or honeycomb structure thatmay reduce the area of electric-conduction layer 102. Theelectric-conduction connecting layer 101 further includes plural viasand plural via plugs. The structure of this electric-conductionconnecting layer 101 may be modified and implemented by those who areskilled in such art according to above disclosure, but it stillpossesses the merits of the invention and is also within the spirit andscope of the invention, so repetitious description is not presentedherein.

In the preferable embodiments according to the invention, the IC padstructure further includes a passivation layer 105, which is arranged onthe insulation layer 500 and is partially connected to the pad layer600. From above design, the compound layer structure 100 is signallyconnected and structured to the pad layer 600, and a steady bonding zoneis thereby formed, such that it may enhance the boding tension andeffectively raise the bonding adherence. Therefore, the tensiongenerated during the bonding procedure to draw the entire structure ofthe IC pad out of the semiconductor chip may be prevented.

In order to further recognize and understand the characteristics,objectives and functions of the present invention, please refer to FIG.6, which is a flowchart illustrating the preferable embodiment of themethod forming the IC pad according to the invention, wherein thenumbers 91, 92, 93, 94 and 95 shown in the drawing respectivelyillustrate the steps from (a) to (e) of the method forming the IC padaccording to the invention.

Step (a): providing a substrate that is arranged with an insulationlayer thereon.

Step (b): forming a lower electric-conduction layer at an appropriateposition in the insulation layer; the lower electric-conduction layer iscomposed of plural electric-conduction layers and pluralelectric-conduction connecting layers. In this embodiment, each of theelectric-conduction layer is interlaced-connected to the correspondingelectric-conduction connecting layers, as shown in FIG. 5, such that asignal connection may be provided to a bond-pad electric-connectionlayer, which further forms a bonding zone with a passivation layer, suchthat the pad layer may be connected to a potential of cleaner powersource or electric potential.

Step (c): a compound layer structure formed on the insulation layer iscomposed of at least one electric-conduction layer and at least oneelectric-conduction connecting layer, each of the electric-conductionlayer is interlaced-connected to the corresponding electric-conductionconnecting layers, as shown in FIG. 5, and the area of theelectric-conduction layer can be reduced by the methods of railingstructure or honeycomb structure, and the electric-conduction connectinglayer further includes the structure of plural vias and plural viaplugs.

Step (d): forming a pad layer on the compound layer structure, whereinthe area of the former is larger than that of the electric-conductionlayer of the latter, and the pad layer is structured as a polygon shape.

Step (e): forming a passivation layer on the insulation layer, such thatthe pad layer may form a bonding zone with the passivation layer.

Accordingly, the structure of an IC pad and its forming method accordingto the invention may indeed reduce the value of equivalent electriccapacitance of the entire pad, separate the noise coming from thesemiconductor substrate, and increase the bonding adherence, so thiskind of designing method may be adapted to integrated circuit of highfrequency and fulfill the requirement of high frequency and low noise.

What is claimed is:
 1. An integrated circuit (IC) device having a padstructure formed thereon, the IC device comprising: a) a substrate; b)an insulation layer formed on the substrate; c) a lowerelectric-conduction layer formed in the insulation layer; d) a compoundlayer structure formed in the insulation layer; e) a first pad layerformed on the insulation layer and coupled to the compound layerstructure, wherein the first pad layer and the compound layer structureare spaced apart from the lower electric-conduction layer; and f) asecond pad layer formed on the insulation layer and coupled to the lowerelectric-conduction layer.
 2. The IC device according to claim 1,wherein the compound layer structure comprises a firstelectric-conduction layer and a first connecting layer to couple thefirst electric-conduction layer to the first pad layer.
 3. The IC deviceaccording to claim 2, wherein the first connecting layer comprises aplurality of via plugs.
 4. The IC device according to claim 2, whereinthe first electric-conduction layer is shaped like a webbed railing. 5.The IC device according to claim 2, wherein the area of the firstelectric-conduction layer is smaller than that of the first pad layer.6. The IC device according to claim 1, wherein the first pad layer isshaped like a polygon.
 7. The IC device according to claim 1, furthercomprising a passivation layer formed on the insulation layer to cover apart of the outer rim of at least one of the first and second padlayers.
 8. The IC device according to claim 1, further comprising atleast one second connecting layer for coupling the second pad layer tothe lower electric-conduction layer.
 9. The IC device according to claim8, further comprising at least one second electric-conduction layercoupled between the second pad layer and the lower electric-conductionlayer with the second connecting layer.
 10. The IC device according toclaim 1, wherein a noise from the substrate is kept away from the firstpad layer by the lower electric-conduction layer.
 11. An integratedcircuit (IC) device having a pad structure formed thereon, the IC devicecomprising: a) a substrate; b) an insulation layer formed on thesubstrate; c) a lower electric-conduction layer formed in the insulationlayer; d) a compound layer structure formed in the insulation layer; ande) a first pad layer formed on the insulation layer and coupled to thecompound layer structure, wherein the first pad layer and the compoundlayer structure are spaced apart from the lower electric-conductionlayer.
 12. The IC device according to claim 11, wherein the compoundlayer structure comprises a first electric-conduction layer and a firstconnecting layer to couple the first electric-conduction layer to thefirst pad layer.
 13. The IC device according to claim 11, furthercomprising a second pad layer formed on the insulation layer and coupledto the lower electric-conduction layer.
 14. The IC device according toclaim 13, further comprising at least one second connecting layer forcoupling the second pad layer to the lower electric-conduction layer;and at least one second electric-conduction layer coupled between thesecond pad layer and the lower electric-conduction layer with the secondconnecting layer.
 15. The IC device according to claim 14, wherein, thearea of the first electric-conduction layer is smaller than that of thefirst pad layer.
 16. The IC device according to claim 11, wherein thefirst pad layer is shaped like a polygon.
 17. The IC device according toclaim 11, further comprising a passivation layer formed on theinsulation layer to cover a part of the outer rim of at least one of thefirst and second pad layers.
 18. The IC device according to claim 11,wherein a noise from the substrate is kept away from the first pad layerby the lower electric-conduction layer.
 19. A method for fabricating anIC device having a pad structure formed thereon, the method comprising:a) providing a substrate; b) forming an insulation layer formed on thesubstrate; c) forming a lower electric-conduction layer formed in theinsulation layer, at least a part of the lower electric-conduction layerbeing covered by the insulation layer; d) forming a compound layerstructure formed in the insulation layer, the compound layer structurebeing spaced apart from and not connected to the lowerelectric-conduction layer; and e) forming a first pad layer formed onthe insulation layer, the first pad layer being coupled to the compoundlayer, wherein in the forming a first pad layer step e) the first padlayer and the compound layer are spaced apart from the lowerelectric-conduction layer.
 20. The method according to claim 19, whereina noise from the substrate is kept away form the first pad layer by thelower electric-conduction layer.
 21. The method according to claim 19,wherein the forming a compound layer structure step d) further comprisesthe steps of: forming at least one first electric-conduction layer onthe insulation layer; and forming at least one first connecting layer onthe insulation layer, wherein the first connecting layer is to couplethe first electric-conduction layer to the first pad layer.
 22. Themethod according to claim 21, wherein the area of the firstelectric-conduction layer is smaller than that of the first pad layer.23. An integrated circuit (IC) device having a pad structure formedthereon, the IC device comprising: a) a substrate; b) an insulationlayer formed on the substrate; c) a plurality of electric-conductionlayers formed in the insulation layer, including a lowerelectric-conduction layer, each electric-conduction layer having athickness; d) a plurality of connecting layers, each connecting layerhaving a thickness, the connection layers interposed between theelectric-conduction layers, the plurality of connecting layersselectively coupling one or more of the electric-conduction layers; e) acompound layer structure formed in the insulation layer; f) a first padlayer formed on the insulation layer and coupled to the compound layerstructure, wherein the first pad layer and the compound layer structureare spaced apart and above from the lower electric-conduction layer,wherein the compound layer structure and the lower electric-conductionlayer are spaced apart by the thickness of at least oneelectric-conduction layer and the thickness of at least one connectinglayer; and g) a second pad layer formed on the insulation layer andcoupled to the lower electric-conduction layer.
 24. The IC deviceaccording to claim 23, wherein the compound layer structure comprises afirst electric-conduction layer and a first connecting layer to couplethe first electric-conduction layer to the first pad layer.
 25. The ICdevice according to claim 24, wherein the first connecting layercomprises a plurality of via plugs.
 26. The IC device according to claim24, wherein the first electric-conduction layer is shaped like a webbedrailing.
 27. The IC device according to claim 24, wherein the area ofthe first electric-conduction layer is smaller than that of the firstpad layer.
 28. The IC device according to claim 23, wherein the firstpad layer is shaped like a polygon.
 29. The IC device according to claim23, further comprising a passivation layer formed on the insulationlayer to cover a part of the outer rim of at least one of the first andsecond pad layers.
 30. The IC device according to claim 23, furthercomprising at least one second connecting layer for coupling the secondpad layer to the lower electric-conduction layer.
 31. The IC deviceaccording to claim 30, further comprising at least one secondelectric-conduction layer coupled between the second pad layer and thelower electric-conduction layer with the second connecting layer.
 32. Anintegrated circuit (IC) device having a pad structure formed thereon,the IC device comprising: a) a substrate; b) an insulation layer formedon the substrate; c) a lower electric-conduction layer formed in theinsulation layer; d) a compound layer structure formed in the insulationlayer; e) a first pad layer formed on the insulation layer and coupledto the compound layer structure, wherein the first pad layer and thecompound layer structure are spaced apart from the lowerelectric-conduction layer; and f) a second pad layer formed on theinsulation layer and coupled to the lower electric-conduction layer,wherein a noise from the substrate is kept away from the first pad layerby the lower electric-conduction layer.
 33. An integrated circuit (IC)device having a pad structure formed thereon, the IC device comprising:a) a substrate; b) an insulation layer formed on the substrate; c) alower electric-conduction layer formed in the insulation layer; d) acompound layer structure formed in the insulation layer; e) a first padlayer formed on the insulation layer and coupled to the compound layerstructure, wherein the first pad layer and the compound layer structureare spaced apart from the lower electric-conduction layer; and f) asecond pad layer formed on the insulation layer and coupled to the lowerelectric-conduction layer.
 34. The IC device according to claim 33,wherein the compound layer structure comprises a firstelectric-conduction layer and a first connecting layer to couple thefirst electric-conduction layer to the first pad layer.
 35. The ICdevice according to claim 33, further comprising at least one secondconnecting layer for coupling the second pad layer to the lowerelectric-conduction layer; and at least one second electric-conductionlayer coupled between the second pad layer and the lowerelectric-conduction layer with the second connecting layer.
 36. The ICdevice according to claim 35, wherein, the area of the firstelectric-conduction layer is smaller than that of the first pad layer.37. The IC device according to claim 33, wherein the first pad layer isshaped like a polygon.
 38. The IC device according to claim 33, furthercomprising a passivation layer formed on the insulation layer to cover apart of the outer rim of at least one of the first and second padlayers.